1. Field of the Invention
The present invention relates to a semiconductor device and a method for manufacturing the same, and more specifically to a semiconductor device having a fine wiring and contact structure, and a method for manufacturing the same.
2. Description of Related Art
With recent increases in integration density of semiconductor devices, the diameter of contact holes has become small, and the width and the spacing of wiring conductor layers electrically connected to the contacts have correspondingly become small. Therefore, in order to realize microminiaturization in the semiconductor device, it has become important that wiring/contact hole margin be made small and that contact resistance be made small in a small contact diameter.
Referring to FIG. 1D, there is shown a conventional wiring and contact structure. A conventional method for forming the conventional wiring and contact structure will be described with reference to FIGS. 1A to 1D illustrating a process of the conventional method.
Firstly, as shown in FIG. 1A, a field oxide film 2 is formed on a p-type silicon substrate 1 by means of a conventional LOCOS (local oxidation of silicon) process, and after a gate oxide film 3 is formed on the substrate, an n-type diffused layer 4 is formed by ion-implanting for example arsenic.
Thereafter, as shown in FIG. 1B, a silicon oxide film is deposited by for example a CVD (chemical vapor deposition) process so as to form a first interlayer insulating film 5A covering the field oxide film 2 and the gate oxide film 3, and then, for example, a tungsten silicide is deposited as a first wiring layer forming material. Thereafter, a photoresist 12 having a predetermined pattern is formed, and an etching is performed using the photoresist 12 as a mask, so as to form a first wiring layer 10. The photoresist 12 is removed.
Then, as shown in FIG. 1C, a silicon oxide film is deposited by for example the CVD process so as to form a second interlayer insulating film 18 covering the first wiring layer 10, the field oxide film 2 and the gate oxide film 3. Then, a photoresist 7 having a predetermined pattern is formed, and the second and first interlayer insulating films 18 and 5A are selectively etched using the photoresist 7 as a mask, so as to form a contact hole, 5B on the n-type diffused layer 4.
Thereafter, as shown in FIG. 1D, a polysilicon film is deposited as a second wiring layer forming material filling the contact hole and covering the second interlayer insulating film 18. Then, a photoresist 19 having a predetermined pattern is formed, and the polysilicon film is etched using the photoresist 19 as a mask, so as to form a second wiring layer 14 electrically connected through the contact hole 5B on the n-type diffused layer 4.
In addition, there have been proposed various improved wiring and contact structures capable of making the integration density higher than that of the conventional multi-layer wiring structure as mentioned just above. Japanese Patent Application Laid-open Publication No. JP-A-63-299142 shows one example of the improved wiring and contact structures. Referring to FIG. 2E, there is shown a sectional view of the improved wiring and contact structure proposed by JP-A-63-299142. FIGS. 2A to 2E are sectional views illustrating the process for manufacturing the improved wiring and contact structure.
In this process, as shown in FIG. 2A, a field oxide film 2 is formed on a p-type silicon substrate 1 by means of a conventional LOCOS process, and then, a gate oxide film 3 is formed on the substrate. Furthermore, an n-type diffused layer 4 is formed by ion-implanting for example arsenic.
Thereafter, a silicon oxide film is deposited by for example a CVD process so as to form a first interlayer insulating film 5A covering the field oxide film 2 and the gate oxide film 3, and then, for example, a tungsten silicide is deposited as a first wiring layer forming material. Furthermore, a photoresist 12 having a predetermined pattern is formed, and the silicide is patterned using the photoresist 12 as a mask, so as to form a first wiring layer 10. The photoresist 12 is removed.
Then, as shown in FIG. 2B, a silicon oxide film is deposited by for example the CVD process so as to form a second interlayer insulating film 18 covering the first wiring layer 10, the field oxide film 2 and the gate oxide film 3. Then, a photoresist 7 having a predetermined pattern is formed, and the second interlayer insulating film 18, the first wiring layer 10, the first interlayer insulating film 5A and the gate oxide film 3 are selectively etched using the photoresist 7 as a mask, so as to form a contact hole 5B which causes a surface of the n-type diffused layer 4 to be exposed.
Thereafter, as shown in FIG. 2C, a silicon oxide film is deposited by for example the CVD process so as to form an insulating film 20, and an anisotropic etching is formed to cause the insulating film 20 to remain only on a side surface of the contact hole 5B, as shown in FIG. 2D.
Then, as shown in FIG. 2E, a polysilicon film is deposited as a second wiring layer forming material filling the contact hole and covering the second interlayer insulating film 18, and then, a photoresist 19 having a predetermined pattern is formed. Furthermore, the polysilicon film is etched using the photoresist 19 as a mask, so as to form a second wiring layer 14 electrically connected through the contact hole 5B on the n-type diffused layer 4 but electrically insulated from the first wiring layer 10.
Furthermore, there has been known to the inventor a structure as shown in FIG. 3, in which a conductor layer 8 connected through a contact hole to an n-type diffused layer 4 is used as a pad for connecting to a second wiring layer 14, so that the contact can overlap a first wiring layer 10. In this connection structure, the first wiring layer 10 is formed on the conductor layer 8 with a second interlayer insulating film 18 being interposed between the conductor layer 8 and the first wiring layer 10, and the second wiring layer 14 is formed on the first wiring layer 10 with a third interlayer insulating film 21 being interposed between the first wiring layer 10 and the second wiring layer 14.
However, the above mentioned conventional connection structures and the conventional methods for manufacturing the same have the following disadvantages:
In the structure shown in FIG. 1D, since an alignment margin is required to prevent a short-circuit between the contact and the first wiring layer, it has been difficult to microminiaturize.
In the structure shown in FIG. 2E, on the other hand, since the insulation between the first wiring layer and the contact is realized by the insulating film which is deposited on the side surface of the contact hole in a self-alignment manner, the margin for alignment between the wiring conductor and the contact hole is no longer required. However, the width of the first wiring layer must be larger than the size of the contact hole, since the first wiring layer would be otherwise open-circuited. Therefore, microminiaturization is very difficult. In addition, since the first wiring layer is made thin at the contact portion, the wiring resistance inevitably increases. In addition, since the size of the contact is reduced by the insulating film deposited on the side surface of the contact hole, and since the contact hole is formed deeply, the contact resistance inevitably increases.
In the conventional example shown in FIG. 3, the photoresist process for forming the pad must be newly added, and since there is required an alignment margin between the first wiring layer 10 and the contact hole connecting the second wiring layer 14 to the pad, it is not a satisfactory structure for realizing.